Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communication networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that boast superior speed performance. This leads IC manufactures to carefully test the speed performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115.
Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 from input pin 130 to output pin 140. The resulting time period is the timing parameter for test circuit 110, the path of interest. Such parameters are typically published in literature associated with particular ICs and/or used to model the speed performance of circuit designs that employ the path of interest.
Test procedures of the type described above are problematic for at least two reasons. First, many signal paths within a given IC are not directly accessible via input and output pins, and therefore cannot be measured directly. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the path of interest is short. For example, if a tester accurate to one nanosecond measures a propagation delay of one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to assume the timing parameter was two nanoseconds, the worst-case scenario. If ICs are not assigned worst-case values, some designs will fail. Thus, IC manufacturers tend to add relatively large margins of error, or “guard bands,” to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost them customers in an industry where speed performance is paramount.
The above-listed inventor and others at Xilinx, Inc., have identified methods and circuits that afford more precise measures of signal propagation delay, and that easily adapt for use with programmable logic devices (PLDs). For example, U.S. Pat. No. 6,075,418 to Kingsley, et al., entitled “System With Downstream Set or Clear for Measuring Signal Propagation Delays on Integrated Circuits,” issued Jun. 13, 2000, describes methods of measuring signal-propagation delays on PLDs by including signal paths of interest in ring oscillators. The ring oscillators oscillate at frequencies that are a function of the delays through signal paths of interest. The oscillation frequencies of such oscillators are therefore indicative of the delays through various paths of interest. The above-referenced patent is incorporated herein by reference.
The methods described in the above-referenced patent work well. Nevertheless, there is always a need for still better approaches to analyzing speed performance, and some circuit configurations are more difficult to measure than others.
FIG. 2 (prior art) depicts a conventional synchronous circuit 200 used here to illustrate a common problem encountered when measuring speed performance on a PLD. Circuit 200 includes a pair of flip-flops 205 and 207 interconnected via some combinatorial logic 210 and a pair of nets 215 and 220.
Data present at the synchronous “D” input terminal of flip-flop 205 is latched into flip-flop 205 at the beginning of each clock cycle. On the same clock cycle, data presented on the synchronous “Q” output terminal of flip-flop 205 is latched into flip-flop 207. Input terminals are synchronous if they are activated by, and therefore synchronous with, a clock signal.
The maximum operating speed of circuit 200 is determined by the clock-to-Q delay of flip-flop 205, the delays associated with nets 215 and 220, the delay through combinatorial logic 210, the set-up time of flip-flop 207, and the clocks skew associated with clock line CLK. Determining the values of the aforementioned delays can be difficult and tedious. Measuring the set-up time of flip-flop 207 is particularly difficult. There is therefore a need for more precise methods and circuits for measuring the timing of critical synchronous paths on programmable logic devices.